Verilog code:
module invert(in,out);
input in;
output out;
assign out=~in;
endmodule
Testbench:
module sim();
reg in;
wire out;
invert innn(in,out);
initial begin
in=0;
#10 in=1;
#20 in=0;
end
endmodule
Saturday, March 5, 2016
Writing first program in Questa Sim(Modelsim)
This tutorial will teach you how you can write your first program and simulate it
Verilog code:
module invert(in,out);
input in;
output out;
assign out=~in;
endmodule
Testbench:
module sim();
reg in;
wire out;
invert innn(in,out);
initial begin
in=0;
#10 in=1;
#20 in=0;
end
endmodule
Verilog code:
module invert(in,out);
input in;
output out;
assign out=~in;
endmodule
Testbench:
module sim();
reg in;
wire out;
invert innn(in,out);
initial begin
in=0;
#10 in=1;
#20 in=0;
end
endmodule
Subscribe to:
Post Comments (Atom)
Hi, this is a very good tutorial, but I need the program. Pls share this program.
ReplyDelete