Writing first program in Questa Sim(Modelsim)

This tutorial will teach you how you can write your first program and simulate it

Verilog code:

module invert(in,out);
  input in;
  output out;
  assign out=~in;

endmodule

Testbench:

module sim();
  reg in;
  wire out;
  invert innn(in,out);
  initial begin
    in=0;
    #10 in=1;
    #20 in=0;
  end

endmodule

Constrained Random Stimulus Generation In System Verilog:

Following are the random functions which are used to generate random number in system verilog

1-$random

2-$urandom() 

3-$urandom_range()

1-$random 

function return a random 32 signed value so this value can be positive or negative

for example

integer d;

 d = $random; 

RESULT: 

d = 303379748; 
d = -1064739199; 

2-$urandom()

 function generates also 32 bit random number but it is always unsigned 

bit [31:0] d;

 d = $urandom(); 

here another option is present you can seed the random function for example

integer seed=3;

int b=$urandom(seed);

It will generate random number but random number remain same throughout the simulation unless one will change the seed value.This function will generate 32 bit fixed random number but if you will change the seed value the random value will also change

what if someone wants to generate random number within specific range let I want to generate random number between 1 to 20, then there is a specific function as given below is used.

int b=$urandom(seed)%20;

this function generate random value b/w 0 and 20;

3-$urandom_range()

it returns the unsigned value b/w specified range its syntax is $urandom_range(max,min);

e.g  $urandom(100,1) 

 this will return value b/w 1 and 100

FINDING THE MODE OF TWO NUMBER

In order to find the mode of two number in verilog one just need to use built-in command which is provided by compiler.

Source code:

module mod(x,y,out );

    input [3:0]x,y; output [3:0] out;

    assign out=x%y;

endmodule

Simulation code:

module test(  );

    reg [3:0]x,y; wire [3:0] out;

    mod dd(x,y,out);

    initial  begin

        #5 x=10;  #5 y= 3;   end

endmodule