In order to find the mode of two number in verilog one just need to use built-in command which is provided by compiler.
Source code:
module mod(x,y,out );
input [3:0]x,y; output [3:0] out;
assign out=x%y;
endmodule
Simulation code:
module test( );
reg [3:0]x,y; wire [3:0] out;
mod dd(x,y,out);
initial begin
#5 x=10; #5 y= 3; end
endmodule
No comments:
Post a Comment