Source Code:
module bcd(bin,bcd);
// I/O Signal Definitions
parameter n=12;// n=32
parameter m=8;//m=27
parameter l=n+m-3;
parameter k=(n+m)/8;
input[n-1:0] bcd;
output reg [m-1:0]bin;
reg[l-1:0]z;
integer i,j;
always @(bcd)
begin
for(i=0; i<l; i=i+1)
begin z[i]=1'b0;end
z[(l-1)-:n]=bcd;
for(i=0;i<m-3;i=i+1)
begin
for(j=0;j<k; j=j+1)
begin
if(z[(m+1+j*4)-:4]>4'b0111)
z[(m+1+j*4)-:4]=z[(m+1+j*4)-:4]-4'b0011;
else
z[(m+1+j*4)-:4]=z[(m+1+j*4)-:4];
end
z=z>>1;
end
bin=z[m-1:0];
end
endmodule
Simulation Code:
module test(
);
reg [11:0]num;
wire [7:0]u;
bcd nn(u,num);
initial
begin
#5 num=324;
#5 num=592;
end
endmodule
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