Source Code:
module periority_encoder(in,valid,out);
input [3:0]in;
output valid;
output [1:0]out;
assign out[0]=in[3]|((~in[2])&in[1]);
assign out[1]=in[3]|in[2];
assign valid=|in;
endmodule
Simulation code:
module test( );
reg[3:0]in;
wire valid;
wire[1:0]out;
integer i;
periority_encoder endf(in,valid,out);
initial
begin
for (i=0; i<16; i=i+1)
#5 in=i;
end
endmodule
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