Source code:
module alu(a,b,sl,carry,out);
input a,b,carry;
output [1:0]out;
input[5:0]sl;
assign out=(sl==5'b000100)? a&b:
(sl==5'b001000)? a&~b:
(sl==5'b001001)? a^b:
(sl==5'b011001)? a+~b+carry:
(sl==5'b010110)? a+b+carry:
2'bzz;
endmodule
Simulation Code:
module test();
reg a;
reg b;
reg [5:0]sl;
reg carry;
wire [1:0]out;
alu aa(a,b,sl,carry,out);
initial begin
#5 a=1;
#5 b=1;
#5 carry=1;
#15 sl= 5'b000100;
#15 sl= 5'b010110;
#15 sl= 5'b001111;
#15 sl= 5'b001001;
end
endmodule
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